Design Flow and Methodology

September 1st – 14:00pm – 15:40pm
Room: Diode
Chair: Andrea Iabrudi Tavares
  • 14:00h: Study Case of Mixed Verification Flow to cope Analog Mixed Signal Mismatch Integration
    • Vinicius Martins, Wang Jiang Chau, Roberto Rangel and Jerson Guex

  • 14:20h: Automatic Synthesis of High-Speed Asynchronous Systems from a Behavioral Specification
    • Kledermon Garcia, Duarte Oliveira, Lester Faria and Orlando Verducci

  • 14:40h: An Approach for De-synchronization: Synthesis of Asynchronous Controllers from Synchronous Design
    • Duarte Oliveira, Higor Delsolto, Orlando Verducci and Lester Faria

  • 15:00h: EDA and IP, a key component of SoC design
    • Terrance Lee Back (Synopsys)